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HI2300
August 1997
8-Bit, 18 MSPS, Video A/D Converter with 3.3V Power Supply Operation
Description
The HI2300 is an 8-bit, CMOS A/D converter for video with synchronizing clamp function and can operate on 3.3V power supply. The adoption of 2 step-parallel method achieves ultra-low power consumption and a maximum conversion speed of 18 MSPS.
Features
* Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit 1/2 LSB (DL) * Maximum Sampling Frequency . . . . . . . . . . . 18 MSPS * Low Power Consumption at 18 MSPS (Typ) (Reference Current Excluded) . . . . . . . . . . . . . . .18mW * Synchronizing Clamp Function * Clamp ON/OFF Function * Reference Voltage Self-Bias Circuit * Input CMOS Compatible * Three-State TTL Compatible Output * Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 3.3V Single * Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 8pF * Reference Impedance . . . . . . . . . . . . . . . . . . 330 (Typ) * Direct Replacement for Sony CXD2300
Ordering Information
PART NUMBER HI2300JCQ TEMP. RANGE (oC) -40 to 85 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S
Applications
* Portable Equipment * Hand-Held Instruments
Pinout
HI2300 (MQFP) TOP VIEW
NC DVSS OE CLE DVSS CCP VREF VRBS D0 D1 D2 D3 D4 D5 D6 D7 3231 30 29 28 27 26 25 1 24 2 23 3 22 4 21 5 20 6 19 18 7 17 8 9 10 11 12 13 14 15 16
VRB AVSS AVSS VIN AVDD AVDD VRT VRTS
TEST DVDD TEST CLK TEST TEST CLP AVDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
4103.1
4-1230
HI2300 Functional Block Diagram
DVSS 28 OE DVSS D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) DVDD TEST (DVDD) CLK 30 31 24 VRB 1 2 3 4 5 6 7 8 16 AVDD 10 11 12 CLOCK GENERATOR LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 19 AVDD UPPER DATA LATCH 18 VRT 17 VRTS 20 AVDD LOWER DATA LATCH LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 23 AVSS 22 AVSS 21 VIN
REFERENCE SUPPLY
25 VRBS
UPPER ENCODER (4-BIT)
UPPER SAMPLING COMPARATOR (4-BIT)
TEST (OPEN) NC
+ 9 32 M-M 29 CLE 27 CCP 26 VREF 15 CLP TEST 14 (V DD OR VSS) TEST 13 (V DD OR VSS)
-
4-1231
HI2300 Pin Descriptions
PIN NUMBER 1 to 8 SYMBOL D0 to D7 EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D7 (MSB) Output.
Di
9
TEST
DVDD 9 DVSS
Leave open during normal usage.
10 12
DVDD CLK
DVDD 12 DVSS
Digital +3.3V. Clock Input.
11, 13, 14
TEST
DVDD 11 13 14 DVSS
Fix Pin 11 to VDD , Pins 13 and 14 to VDD or VSS during normal usage.
15
CLP
DVDD 15
Inputs Clamp Pulse to Pin 15 (CLP). Clamps the signal voltage during Low interval.
DVSS
16, 19, 20 17
AVDD VRTS
AVDD
Analog +3.3V Generates approximately +1.8V when shorted with VRT .
17
18 24
VRT VRB
18
AVDD
Reference Voltage (Top). Reference Voltage (Bottom).
24
AVSS
4-1232
HI2300 Pin Descriptions
PIN NUMBER 21 (Continued) EQUIVALENT CIRCUIT
AVDD
SYMBOL VIN
DESCRIPTION Analog Input.
21
AVSS
25
VBRS
AVSS
Generates approximately +0.4V when shorted with VRB .
25
26
VREF
AVDD
Clamp Reference Voltage Input. Clamps so that the reference voltage and the input signal during clamp interval are equal.
26
AVSS
27
CCP
AVDD
Integrates the clamp control voltage. The relationship between the changes in CCP voltage and in VIN voltage is positive phase.
27
AVSS
28, 31 29
DVSS CLE
DVDD
Digital Ground. The clamp function is enabled when CLE = Low. The clamp function is set to off and the converter functions as a normal A/D converter when CLE = High. The clamp pulse can be measured by connecting CLE to DVDD through a several-hundred-ohm resistor.
CLAMP PULSE
29
DVSS
30
OE
DVDD
Data is output when OE = Low. Pins D0 to D7 are at high impedance when OE = High.
30
DVSS
32
NC
No Connect pin.
4-1233
HI2300
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Analog Input (ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . VRT to VRB Clock Pulse width (tPW1) . . . . . . . . . . . . . . . . . . . . . . . . 27ns (Min) (tPW0). . . . . . . . . . . . . . . . . . . . . . . . . 27ns (Min)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage (VRT , VRB) . . . . . . . . . .VDD +0.5V to VSS - 0.5V Input Voltage, Analog (VIN) . . . . . . . . . . . .VDD +0.5V to VSS - 0.5V Input Voltage, Digital (VIH , VIL) . . . . . . . . .VDD +0.5V to VSS - 0.5V Output Voltage, Digital (VOH , VOL) . . . . . .VDD +0.5V to VSS - 0.5V
Recommended Operating Conditions
Temperature Range (tOPR) . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage (IDVSS - AVSSI). . . . . . . . . . . . . . . . . . . 0 to 100mV Power Supply (DVDD , DVSS)(AVDD , AVSS). . . . . . . . .3.14V to 4.0V Reference Input Voltage (VRB). . . . . . . . . . . . . . . . . . . . . . . . . 0.4V (VRT) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Maximum Conversion Rate Minimum Conversion Rate Supply Current Reference Pin Current Analog Input Band Width Analog Input Capacitance
When using a single power supply; fC = 18 MSPS, VDD = 3.3V, VRB = 0V, VRT = 1.5V, TA = 25oC SYMBOL fC Max fC Min IDD IREF BW CIN RREF VRB1 VRT1 - VRB1 EOT EOB VIH VIL IIH IIL IOH IOL IOZH IOZL tDL tPZH tPZL tPHZ tPLZ EL ED tAJ tSD EOC tCPD VIN = DC PWS = 3s VREF = 0.5V VREF = 1.5V VDD = Max OE = VSS VDD = Min OE = VDD VDD = Max VIH = VDD VIL = 0V VOH = VDD - 0.5V VOL = 0.4V VOH = VDD VOL = 0V Shorts VRB and VRBS Shorts VRT and VRTS VIN = 1.4VP-P , 17.9MHz VIN = 0.75V + 0.07 VRMS TEST CONDITIONS VIN = 0 to 1.5V fIN = 1kHz Ramp fC = 18 MSPS, NTSC Ramp Wave Input MIN 18 3.3 230 0.33 1.30 -45 40 2.5 -1.0 3.3 8 TYP 32 32 5.5 4.6 -.9 8 330 0.36 1.39 -25 60 18 MAX 0.5 10 6.6 440 0.39 1.48 -5 80 0.5 5 16 16 30 UNITS MSPS MSPS mA mA dB pF V V mV mV V V A A mA mA A A ns
Reference Resistance (VRT to VRB) Self Bias I Offset Voltage Digital Input Voltage Digital Input Current Digital Output Current Digital Output Current Output Data Delay Three-State Output Enable Time Three-State Output Disable Time Integral Nonlinearity Error Differential Nonlinearity Error Aperture Jitter Sampling Delay Clamp Offset Voltage Clamp Pulse Delay
With TTL 1 Gate and 10pF Load RL = 1k, CL = 20pF, OE = 3V0V RL = 1k, CL = 20pF, OE = 0V3V fC = 18 MSPS VIN = 0 to 1.5V fC = 18 MSPS VIN = 0 to 1.5V
-20 -30 -
+0.5 0.3 30 4 0 -10 25
1.3 0.5 +20 +10 -
LSB LSB ps ns mV mV ns
4-1234
HI2300
Digital Output The following table shows the relationship between analog input voltage and digital output code.
DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE VRT * * * * * * * * VRB STEP 0 * * * 127 128 * * * 255 0 0 0 0 1 0 0 1 0 1 0 1 * * * 0 0 0 0 MSB 1 1 1 1 * * * 0 1 0 1 0 1 0 1 1 1 LSG 1 1
Timing Chart
tPW1 tPW0
CLOCK
ANALOG INPUT
N
N+1
N+2
N +3
N+4
DATA OUTPUT
N-3 tD tD = 18ns
N-2
N-1
N
N-1
: Analog Sampling Point
4-1235
HI2300 Typical Application Circuits
HC04 CLOCK IN CLAMP PULSE IN LATCH CK (NOTE 2) Q 0.01 +3.3V (ANALOG) 17 18 19 VIDEO IN 10 75 + 10p 0.1 20 21 22 23 0.01 +3.3V (ANALOG) VREF 20K GND (ANALOG) 0.01 GND (DIGITAL) 24 25 26 27 28 29 30 31 32 OPEN 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 +3.3V (DIGITAL) 0.1
NOTE: 1. The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operaiotn. However, slight small beat may be generated as Vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. At such time, the latch circuit is efective in this case. FIGURE 1. WHEN CLAMP IS USED (SELF BIAS)
+3.3V (DIGITAL) HC04 CLOCK IN 16 0.01 +3.3V (ANALOG) 17 18 19 VIDEO IN 10 75 + 10p 0.1 20 21 22 23 0.01 24 25 26 27 28 29 30 31 32 DAC, PWM, ETC. GND (DIGITAL) GND (ANALOG) INFORMATION OTHER THAN CLAMP INTERVAL IS AT HIGH IMPEDANCE. 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 1 SUBTRACTER, COMPARATOR, ETC. CLAMP LEVEL SETTING DATA 0.1
0.01
NOTES: 2. The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase. 3. VIN/VCCP = 3.0 (fS = 20 MSPS). FIGURE 2. DIGITAL CLAMP (SELF BIAS)
4-1236
HI2300 Typical Application Circuits
(Continued)
+3.3V (DIGITAL) HCO4 CLOCK IN OPEN 16 17 +3.3V (ANALOG) 0.01 18 19 VIDEO IN 75 21 0.1 22 10p 23 0.01 24 25 26 27 28 29 30 31 32 1 D0 2 D1 3 D2 4 D3 20 7 6 5 D6 D5 D4 15 14 13 12 11 10 9 8 D7 0.1
+3.3V (DIGITAL) GND (ANALOG) GND (DIGITAL)
FIGURE 3. WHEN CLAMP IS NOT USED (SELF BIAS)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-1237

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